8 Bit Parallel In Serial Out Shift Register Vhdl Code

In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the 'data' input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the 'bit array' stored in it, 'shifting in' the data present at its input and 'shifting out' the last bit in the array, at each transition of the clock input.

May 13, 2014  74HC165 Parallel in, Serial Out Shift Register. Some of the features of 74HC165: 8 bit Parallel Input; Serial output; Can be cascaded/ daisy chained; For more details on the chip, please refer to the datasheet here. 74HC165 Pin Diagram Pin Description. The input pins of the shift registers are pin 11 to 14 (D0 to D3) and pin 3 to pin 6 (D4 to D7).

More generally, a shift register may be multidimensional, such that its 'data in' and stage outputs are themselves bit arrays; this is implemented simply by running several shift registers of the same bit-length in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are often configured as 'serial-in, parallel-out' (SIPO) or as 'parallel-in, serial-out' (PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are also 'bidirectional' shift registers which allow shifting in both directions: L→R or R→L. The serial input and last output of a shift register can also be connected to create a 'circular shift register'. A PIPO register (parallel in, parallel out) is very fast – an output is given within a single clock pulse.

Serial-in serial-out (SISO)[edit]

Destructive readout[edit]

These are the simplest kind of shift registers. The data string is presented at 'Data In', and is shifted right one stage each time 'Data Advance' is brought high. At each advance, the bit on the far left (i.e. 'Data In') is shifted into the first flip-flop's output. The bit on the far right (i.e. 'Data Out') is shifted out and lost.

The data is stored after each flip-flop on the 'Q' output, so there are four storage 'slots' available in this arrangement, hence it is a 4-bit Register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As 'Data In' presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at 'Data Advance' each time—this is called clocking or strobing) to the register, this is the result. The right hand column corresponds to the right-most flip-flop's output pin, and so on.

So the serial output of the entire register is 00001011. It can be seen that if data were to be continued to input, it would get exactly what was put in (10110000), but offset by four 'Data Advance' cycles. This arrangement is the hardware equivalent of a queue. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high.

This arrangement performs destructive readout - each datum is lost once it has been shifted out of the right-most bit.

Serial-in parallel-out (SIPO)[edit]

This configuration allows conversion from serial to parallel format. Data input is serial, as described in the SISO section above. Once the data has been clocked in, it may be either read off at each output simultaneously, or it can be shifted out.

In this configuration, each flip-flop is edge triggered. All flip-flops operate at the given clock frequency. Each input bit makes its way down to the Nth output after N clock cycles, leading to parallel output.

In cases where the parallel outputs should not change during the serial loading process, it is desirable to use a latched or buffered output. In a latched shift register (such as the 74595) the serial data is first loaded into an internal buffer register, then upon receipt of a load signal the state of the buffer register is copied into a set of output registers. In general, the practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires.

Parallel-in serial-out (PISO)[edit]

This configuration has the data input on lines D1 through D4 in parallel format, D1 being the most significant bit. To write the data to the register, the Write/Shift control line must be held LOW. To shift the data, the W/S control line is brought HIGH and the registers are clocked. The arrangement now acts as a PISO shift register, with D1 as the Data Input. However, as long as the number of clock cycles is not more than the length of the and 'shift left' the data in a register, effectively dividing by two or multiplying by two for each place shifted.

Very large serial-in serial-out shift registers (thousands of bits in size) were used in a similar manner to the earlier delay line memory in some devices built in the early 1970s. Such memories were sometimes called 'circulating memory'. For example, the Datapoint 3300 terminal stored its display of 25 rows of 72 columns of upper-case characters using fifty-four 200-bit shift registers, arranged in six tracks of nine packs each, providing storage for 1800 six-bit characters. The shift register design meant that scrolling the terminal display could be accomplished by simply pausing the display output to skip one line of characters.^[1]

History[edit]

One of the first known examples of a shift register was in the Mark 2 Colossus, a code-breaking machine built in 1944. It was a six-stage device built of vacuum tubes and thyratrons.^[2] A shift register was also used in the IAS machine, built by John von Neumann and others at the Institute for Advanced Study in the late 1940s.

See also[edit]

• Linear feedback shift register (LFSR)
• SerDes (Serializer/Deserializer)
• Shift register lookup table (SRL)

References[edit]

1. ^bitsavers.org, DataPoint 3300 Maintenance Manual, December 1976.
2. ^Flowers, Thomas H. (1983), 'The Design of Colossus', Annals of the History of Computing, 5 (3): 246, doi:10.1109/MAHC.1983.10079

Overview

Using this 8-bit shift register is a convenient way to map a serial stream of signals to parallel output. But what exactly does this mean, and when is it useful? We will try to answer these questions below, as well as give you an example application of where the shift register came in handy.

How it Works

The shift register requires a minimum of three stamp pins to operate. One pin is used as input, one for a clock signal, and one for a clear signal. All operations happen on the leading edge of the clock signal. Values are passed down the line of outputs with each cycle of the clock.. This will hopefully become clearer with the following diagrams.

Both the input and clear signals can be wired directly to stamp pins. Setting the the clear pin to low will cause all the outputs of the shift register to be low. Setting the clear pin to high enables you to change the values on the output puts using the clock signal and input as described later on.

The Basic Stamp is capable of generating a clock signal by using the PWM (Pulse-Width-Modulation) command. For example:

PWM 7, 255, 8

will pulse out a clock signal between 0V and +5V for 8 cycles on PIN7. The wave produced can be visualized as:

With each pulse, the input signal (which can be a connection to a Pin on the basic stamp, set to high or low) shifts the previous signals down the register and sets Qa. If, for example, you want the output (Qa-Qh) of the shift register to equal 11000001, the code might look something like the following:

'set the last three pins as output
PINS = %11100000

'give the pins meaningful symbols
SYMBOL input = PIN5
SYMBOL clear = PIN6
SYMBOL clock = PIN7

'set the clear to high
HIGH clear

'set input to high for last 1
HIGH input

H-x diagramm word mojo gold online for mac 2017. 'pulse out one clock signal
PWM clock, 255, 1

'pulse out the 5 zeros
LOW input
PWM clock, 255,5

'pulse out two more ones
HIGH input
PWM clock, 255,2

The shift register has D-Type flip-flops on the outputs. This means that once you set the output high/low, it will maintain that value. The only way to change it is to set clear to low (which clears all outputs) or shift a new set of values down the outputs.

Here is a link to the technical documentation for the MM74HCT164 shift register: MM74HCT164.pdf

Sample Application

In the Superficial Surface project, we had a lot of inputs and outputs. Since we were limited by the number of pins on a basic stamp, we used the 8-bit Shift register to 'demux' a signal to multiple outputs. By using the register, we were able to control 7 outputs with only 3 stamps pins. With an additional shift-register, we could have easily controlled 14 outputs off the same 3 pins!

Circuit with 1 Shift Register

Circuit with 2 Shift Registers

Our problem was that we wanted to control 12 valves from a single stamp. Since the stamp only has at most, 8 output pins, we had to come up with a better solution. The shift register allowed us to multiplex a signal to a set of relays which triggered our valves. We could turn on and off each valve by setting the input, shifting the bit down the register, and stopping when the correct sequence was in place.

To add an additional 7 outputs, all that is needed is another MM74HCT164. Wire the Qh pin of the first register to the inputs (A1, A2) of the second register, connect the clock pins on both registers to the same stamp pin, connect the clear pins on both registers to the same stamp pin. The values move down the first register and the clock signal oscillates. When a value reaches Qh on the first register, it is transferred to the the second register and continues on.

Problems That We Ran Into

When we first hooked up the shift-register, we were only attached to one of the input pins (A1). This caused a lot of strange behavior since the register requires both inputs to operate correctly. For our purposes, it was easiest to just connect both inputs together. It is also possible to hook in separate sources to the two inputs in which case the signals are logically 'AND'ed together to produce the value which will be shifted down the outputs.

You have to make sure that all the pins are set to output as in the sample code above. We forgot to set them as such when we first hooked up the shift-register and were confused as to why nothing was working.

Tip: you don't always have to shift in multiples of 8. We were only interested in firing one relay at a time so in our code we set the clear bit to low to clear all the pins, set the clear back to high, set input to high, and then PWM only as many times as we needed to fire the appropriate relay. The pulses happen so fast that only the relay we were interest in actually got fired. Intermediate firing of the relays did not occur as the clock signal propagated values down the outputs.